3 Flip Flops Flip Flops One - hot Non - one - hot Decode Non - one - hot Encoded one - hot One - hot O / P &

1. Introduction Among the different design for testability (DFT) techniques available today, scan path based methods [Williams 83] are probably the most basic and most widely used. In a scan-path based design, the circuit has two operating modes; the normal functional mode and test mode during which the circuit bistables are interconnected into a shift register. Thus, in the test mode, it is possible to shift an arbitrary test pattern into the bistables. By returning the circuit to normal mode for one clock period, the outputs of the combinational circuitry are stored in the bistables. If the circuit is then placed into test mode, it is possible to shift out the contents of the bistables and compare these contents with the correct response [McCluskey 86]. Thus, a sequential circuit is transformed into a combinational one during testing thereby making test generation simpler. Many circuits contain logic that is controlled by mutually exclusive (one-out-of-n) input signals. A typical example is an n-to-1 multiplexer implemented with n transmission gates, each controlled (enabled) by a mutually exclusive control signal. Unfortunately, the presence of such circuits poses a problem in scan-based or BIST designs. At any point during the scan process, the bistables may contain a state that is invalid during functional operation, resulting in non-mutually exclusive values on the control signals. This can result in abnormal (unpredictable) behavior of the entire circuit. In designs containing tristate buses, the presence of non-mutually exclusive values in the tristate control inputs may cause damage to the circuit. The goal of our synthesis technique is to generate designs that are safe for scan and BIST operations in the presence of mutually exclusive signals. In general, our technique generates designs with less area than the conventional technique of synthesizing such designs without taking in account safety during scan or BIST operations. Different approaches have been proposed for handling one-hot latches (latches that are supposed to contain mutually exclusive values) in a scan path based design. The simplest is to remove such latches from the scan path thereby resulting in a partial-scan design [Cheng 90][Lee 90][Abramovici 91]. Another approach gates the output of the mutually exclusive latches during scanning, resulting in a particular set of mutually exclusive values enforced on the latch outputs irrespective of its contents. Another way of circumventing this problem is to remove these system latches from the scan chain and use a set of shadow …